The present invention relates to a method for forming a wiring structure in a semiconductor device.
As a conventional method for forming a wiring structure, there has been used one disclosed in, e.g., Japanese Laid-Open Patent Publication No. HEI 10-214834. Referring to the drawings, the conventional method for forming a wiring structure will be described by using, as an example, the case where plugs are formed in holes formed in an insulating film.
FIGS. 8A to 8C are cross-sectional views illustrating the individual process steps of the conventional method for forming a wiring structure.
First, as shown in FIG. 8A, a silicon dioxide film 12 having a thickness of about 1 μm is deposited as an insulating film on a silicon substrate 11. Then, holes 13 each having a diameter of about 0.8 μm are formed by lithography and dry etching in specified regions of the silicon dioxide film 12 to extend therethrough. Next, a titanium film 14 having a thickness of 30 nm and serving as a lower-layer conductive film and a titanium nitride film 15 having a thickness of 100 nm and serving as an interlayer conductive film are deposited successively by PVD (physical vapor deposition) over the entire surface of the silicon dioxide film 12 including the holes 13. Thereafter, a tungsten film 16 having a thickness of 1 μm and serving as an upper-layer conductive film is deposited by CVD (chemical vapor deposition) over the entire surface of the titanium nitride film 15, whereby a conductive film having a three-layer structure is deposited. In the three-layer conductive film, each of the titanium film 14 and the titanium nitride film 15 is a barrier metal.
Next, the respective portions of the tungsten film 16 and the titanium nitride film 15 deposited on regions outside the holes 13 are removed by chemical mechanical polishing (CMP) using an abrasive agent, as shown in FIG. 8B. This completely exposes the portions of the titanium film 14 deposited on the regions outside the holes 13.
Next, the portions of the titanium film 14 deposited on the regions outside the holes 13 are removed by CMP using another abrasive agent, as shown in FIG. 8C. This forms plugs 17 composed of tungsten in the holes 13 and exposes the silicon dioxide film 12.
Although the formation of tungsten plugs has been described above by way of example, it is also possible to form, e.g., copper wires in wiring grooves formed in an insulating film by the same method. With the scaling down of a wiring pattern, the spacing between adjacent wires (wire-to-wire spacing) has been reduced increasingly so that an anti-reflection layer (hereinafter referred to as ARL) has been used in a lithographic step for forming wiring grooves, via holes, and the like.
However, the formation of wires using an ARL film based on the foregoing conventional method for forming a wiring structure has the problem that a short circuit occurs between wires.